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| EtronTech Features * Organized as 1M words by 16 bits * Fast Cycle Time : 70ns * Standby Current : 100uA * Deep power-down Current : 10uA (Memory cell data invalid) * Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15) * Compatible with low power SRAM * Single Power Supply Voltage : 3.0V0.3V * Package Type : 48-ball FBGA, 6x8mm EM566168 1M x 16 Pseudo SRAM Preliminary, Rev 0.2 Apr. 2002 Pin Assignment 48-Ball BGA, Top View 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CE2 B DQ8 UB# A3 A4 CE1# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 Pin Description Symbol A0 - A19 DQ0 - DQ15 CE1# CE2 OE# WE# LB# UB# VCC VSS Function Address Inputs Data Inputs/Outputs Chip Enable Deep Power Down Output Enable Write Control Lower Byte Control Upper Byte Control Power Supply Ground D VSS DQ11 A17 A7 DQ3 VCC E VCC DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 NC Overview The EM566168 is a 16M-bit Pseudo SRAM organized as 1M words by 16 bits. It is designed with advanced CMOS technology specified RAM featuring low power static RAM compatible function and pin configuration. This device operates from a single power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when CS1# or both UB# and LB# are asserted high or CS2 is asserted low. There are three control inputs. CS1# and CS2 are used to select the device, and output enable (OE#) provides fast memory access. Data byte control pins (LB#,UB#) provide lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed wide operating range, the EM566168 can be used in environments exhibiting extreme temperature conditions. Pin Location Symbol A0 A1 A2 A3 A4 A5 A6 A7 Location A3 A4 A5 B3 B4 C3 C4 D4 Symbol A8 A9 A10 A11 A12 A13 A14 A15 Location H2 H3 H4 H5 G3 G4 F3 F4 Symbol A16 A17 A18 A19 NC DQ0 DQ1 DQ2 Location E4 D3 H1 G2 H6 B6 C5 C6 Symbol DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 Location D5 E5 F5 F6 G6 B1 C1 C2 Symbol DQ11 DQ12 DQ13 DQ14 DQ15 CE1# CE2 OE# Location D2 E2 F2 F1 G1 B5 A6 A2 Symbol WE# LB# UB# VCC VCC GND GND NC Location G5 A1 B2 D6 E1 D1 E6 E3 Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Block Diagram Standby/Deep Power Down Mode Control EM566168 VCC VSS Refresh Control Memory Cell Array Refresh Counter Row Address Decoder 1M x 16 A0 - A19 Address Buffer DQ0 - DQ7 DQ8 - DQ15 Input Data Control Sense AMP Output Data Control Column Decoder Address Buffer CS1# CS2 OE# WE# LB# UB# Control Logic Preliminary 2 Rev 0.2 Feb. 2002 EtronTech Operating Mode CS1# CS2 OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15 H X L L L L L L L L L H L H H H H H H H H H X X X H H L L L X X X X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L High-Z High-Z High-Z High-Z High-Z D-out High-Z D-out D-in High-Z D-in High-Z High-Z High-Z High-Z High-Z High-Z D-out D-out High-Z D-in D-in Mode Deselect Deselect Deselect Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write EM566168 Power Standby Deep Power Down Standby Active Active Active Active Active Active Active Active Note: X=don't care. H=logic high. L=logic low. 1) Absolute Maximum Ratings Supply voltage, VCC Input voltages, VIN -0.2 to +3.6V -0.2 to VCC + 0.3V -2.0 to +3.6V* 100 mA -25 to +85C -65 to +125C 240C 1W Input and output voltages, VIN, VOUT Output short circuit current ISH Operating temperature, TA Storage temperature, TSTRG Soldering Temperature (10s), TSOLDER Power dissipation, PD Note: Absolute maximum DC requirements contains stress ratings only. Functional operation at the absolute maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability. Recommended DC Operating Conditions Symbol VCC VSS VIH VIL Notes: 1. Overshoot: VCC + 2.0V in case of pulse width 20ns 2. Undershoot: -2.0V in case of pulse width 20ns 3. Overshoot and undershoot are sampled, not 100% tested. Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.2 2) Typ. 3.0 - - - Max. 3.3 0 VCC+0.2 +0.6 1) Unit V V V V Preliminary 3 Rev 0.2 Feb. 2002 EtronTech DC Characteristics Symbol ILI Parameter Input Leakage Current Test Conditions VIN = VSS to VDD VIO = VSS to VDD CE1# = VIH, CE2 = VIL or OE# = VIH or WE# = VIL Cycle time = Min., 100% duty ICC1 Operating Current @ Min Cycle Time IIO = 0mA, CE1# = VIL, CE2 = VIH, VIN = VIH or VIL Cycle time = 1s, 100% duty ICC2 Operating Current @ Max Cycle Time (1s) IIO = 0mA, CE1# 0.2V, CE2 VDD -0.2V, VIN 0.2V or VIN VDD -0.2V CE1# = VDD - 0.2V and ISB1 Standby Current (CMOS) CE2 = VDD - 0.2V, Other inputs = VSS ~ VCC ISBD VOL VOH Deep Power Down Output Low Voltage Output High Voltage CE2 0.2V, Other inputs = VSS ~ VCC IOL = 2.1mA IOH = -1.0mA - 2.4 - - - Min. -1 EM566168 Max. 1 Unit A ILO Output Leakage Current -1 1 A 25 mA 3 mA 100 A 10 0.4 - A V V Capacitance (Ta = 25C; f = 1 MHz) Parameter Input capacitance Output capacitance Symbol CIN COUT Min - - Typ - - Max 8 10 Unit pF pF Test Conditions VIN = GND VOUT = GND Notes: These parameters are sampled and not 100% tested. Preliminary 4 Rev 0.2 Feb. 2002 EtronTech Symbol Parameter Min Read Cycle tRC tAA tCO1 tCO2 tOE tBA tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH tWC tWP tAW tCW tBW tAS tWR tWHZ tOW tDW tDH Read cycle time Address access time Chip Enable (CE1#) Access Time Chip Enable (CE2) Access Time Output enable access time Data Byte Control Access Time Chip Enable Low to Output in Low-Z Output enable Low to Output in Low-Z Data Byte Control Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Data Byte Control High to Output in High-Z Output Data Hold Time Write Cycle Write Cycle Time Write Pulse Width Address Valid to End of Write Chip Enable to End of Write Data Byte Control to End of Write Address Setup Ttime Write Recovery Time WE# Low to Output in High-Z WE# High to Output in Low-Z Data to Write Overlap Data Hold Time 85 60 70 70 70 0 0 - 5 30 0 - - - - - - - 30 - - - 70 50 60 60 60 0 0 - 5 30 0 85 - - - - - 10 5 10 - - - 10 - 85 85 85 40 85 - - - 35 35 35 - 70 - - - - - 10 5 10 - - - 10 -85 Max Min EM566168 -70 Max AC Characteristics and Operating Conditions (Ta = -25C to 85C, VCC = 2.7V to 3.3V) Unit - 70 70 70 35 70 - - - 25 25 25 - - - - - - - - 20 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AC Test Condition * Output load : 50pF + one TTL gate * Input pulse level : 0.4V, 2.4 * Timing measurements : 0.5 x VCC * tR, tF : 5ns Preliminary 5 Rev 0.2 Feb. 2002 EtronTech AC Test Loads RL = 50 DOUT Z0 = 50 Note: 1. Including scope and jig capacitance CL = 50 pF 1 EM566168 VL = 1.5 V State Diagram Deep Power Down Exit Sequence CE1# = VIH or VIL, CE2=VIH Deep Power Down Mode CE2=VIL CE1# =VIH or VIL, CE2=VIH Power on Initial State (Wait 200s) Active CE2=VIH, CE1# =VIH or UB#, LB# =VIH CE2=VIL Power Up Sequence CE1# =VIL, CE2=VIH, UB# & LB# or/and LB# = VIL Standby Mode Standby Mode Characteristics Power Mode Standby Deep Power Down Memory Cell Data Valid Invalid Standby Current (A) 100 10 Wait Time (s) 0 200 Preliminary 6 Rev 0.2 Feb. 2002 EtronTech Timing Diagrams Read Cycle 1 - Addressed Controlled 1) EM566168 tRC Address tAA tOH Data Out Previous Data Valid tOH Data Valid Read Cycle 2 - CS1# Controlled 2) tRC Address tAA tCO CE1# tLZ tHZ tBA UB#, LB# tBLZ tBHZ tOH tOE OE# tOLZ Data Out High-Z tOHZ Data Valid High-Z Notes: 1. CE1# = OE# = VIL, CE2 = WE# = VIH, UB# or/and LB# = VIL 2. CE2 = WE# = VIH Preliminary 7 Rev 0.2 Feb. 2002 EtronTech Write Cycle 1 - WE# Controlled 1) 2) EM566168 tWC Address tAW CE1# tCW tWR UB#, LB# tBW WE# tAS High-Z tWP tDW Data Valid tWHZ tOW tDH High-Z Data In Data Out Data Undefined Write Cycle 2 - CS1# Controlled 1) 2) tWC Address tAW tAS CE1# tCW tWR UB#, LB# tBW WE# tWP tDW tDH Data In Data Valid Data Out High-Z Preliminary 8 Rev 0.2 Feb. 2002 EtronTech Write Cycle 3 - UB#, LB# Controlled 1) 2) EM566168 tWC Address tAW CE1# tCW tWR UB#, LB# tAS tBW WE# tWP tDW tDH Data In Data Valid Data Out High-Z Notes: 1. CE2 = VIH 2. CE2 = WE# = VIH Preliminary 9 Rev 0.2 Feb. 2002 EtronTech Deep Power Down Mode 200s EM566168 Read Operation Twice or Stay High during 300s = = CE2 1s Normal Operation Suspend Mode Deep Power Down Mode Wake Up Normal Operation = = CE1# Power Up 1 Read Operation Tiwce 200s = = VCC CE2 CE1# Power Up 2 (No Dummy Cycle) 200s 300s = = = = VCC CE2 CE1# Preliminary 10 Rev 0.2 Feb. 2002 EtronTech Avoid Timing EM566168 Etron Pseudo SRAM has a timing which is not supported at read operation. If your system has multiple invalid address signal shorter than tRC during over 15s at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15 s shown as in Avoidable timing 1 or toggle CE1# to high ( tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing CE1# 15s WE# < tRC Address Avoidable Timing 1 CE1# 15s WE# tRC Address Avoidable Timing 2 15s CE1# tRC WE# < tRC Address Preliminary 11 Rev 0.2 Feb. 2002 EtronTech Package Diagrams 48-Ball BGA Units in mm TO P V IE W EM566168 B O T T O M V IE W 0.0 75 S S C C P IN 1 C O R N E R 0 .1 5 P IN 1 C O R N E R A B 0.3 0 3 4 5 6 6 5 4 3 0 .0 5 (4 8 X) 2 1 1 2 8.0 0.1 -B- 0.02 0 .7 5 3 .7 5 0.52 0.03 -A6.0 0.1 0.23 0 .1 2 M A X -C0.15 1.20 MAX S E A T IN G P L A N E Preliminary 0.32 0.05 0.04 12 Rev 0.2 Feb. 2002 |
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